Some industry observers have questioned the move towards 12 inch substrates, as 6-inch substrate manufacturers are still embroiled in fierce price wars and the research and development progress of 8-inch substrates continues to lag behind. However, supply chain executives believe that this layout is commercially reasonable. Different application scenarios face different barriers. Currently, the vast majority of 6-inch and 8-inch silicon carbide wafers are used for electric vehicles and solar equipment, which are being squeezed by fierce price competition in the Chinese market. On the contrary, advanced packaging of AI chips targets product areas with higher profit margins, where thermal control is crucial. The technical requirements for CoWoS applications are relatively relaxed. The 12 inch silicon carbide heat dissipation substrate required for packaging has a specification lower than that of power device wafers. This enables silicon carbide suppliers to avoid the technical challenges faced by 6-inch and 8-inch substrates in crystal growth, cost, and processing, and directly enter the higher value packaging application field. Industry insiders predict that the application of 12 inch silicon carbide substrates in this field will be promoted in two stages: first, using polycrystalline substrates to achieve heat dissipation function, and then turning to single crystal silicon carbide intermediate layers around 2027. Phase 1: Polycrystalline Heat Dissipation Substrate It is reported that the initial application of polycrystalline silicon carbide substrate replacing ceramic heat dissipation substrate has been launched on a small scale. This type of polycrystalline substrate is produced using chemical vapor deposition (CVD) process, without the need for epitaxial steps. Due to the fact that this type of substrate is only used for thermal management, the requirements for electrical performance indicators are relatively low. But the main challenge faced by manufacturers is to achieve semiconductor level flatness - its accuracy needs to reach Å level. Enterprises with advanced cutting, grinding, and polishing capabilities have the most competitive advantage in this stage. Phase 2: Single crystal silicon carbide interlayer is expected to be launched around 2027, replacing the silicon interlayer with a single crystal silicon carbide layer. This material has both high thermal conductivity and high electrical resistivity characteristics. Compared to heat dissipation substrates, this type of application requires higher material complexity and technical accuracy. Suppliers are exploring different technological paths. GlobalWafers has initiated sample testing of monocrystalline silicon carbide products, while Hermes Epitek, a crystal growth and equipment manufacturer, is testing alternative solutions based on chemical vapor deposition (CVD). Both companies are committed to developing 12 inch wafers that meet the uniformity requirements of AI chip packaging structures. Analysts remind that silicon carbide is still one of the candidate materials in the CoWoS thermal management field. Wafer foundries typically make multiple specification requirements to suppliers simultaneously, leaving room for competitive solutions. Nevertheless, the supply chain in Taiwan, China has begun to take action. From crystal growth, wafer processing to equipment manufacturing, related companies are preparing for potential large-scale applications, betting that the surging demand for AI will inject new vitality into the silicon carbide industry that has suffered setbacks for years.